1. Field of the Invention
This invention relates to an analog-to-digital (A-D) converter, and more particularly to a voltage-time conversion type A-D converter or an integration type A-D converter.
2. Description of the Prior Art
A voltage-time conversion type A-D converter as shown in FIG. 5 is generally known. For example, a system block diagram of such a circuit is shown in FIG. 1, page 101 of Japanese publication "Transistor Gijutsu" issued January 1975.
In FIG. 5, a capacitor C.sub.o and a switching transistor Q.sub.o are connected in parallel with each other and between a constant current source I.sub.o and the ground potential to form a charging and discharging circuit. The other end of the constant current source I.sub.o is connected to a supply voltage source terminal V.sub.cc. A comparator A.sub.o has a positive input terminal connected to an input terminal V.sub.in applied with an analog input voltage and a negative input terminal connected to the interconnection point of the constant current source I.sub.o and the charging and discharging circuit to be applied with the output of the charging and discharging circuit. The switching transistor Q.sub.o of the charging and discharging circuit is driven by a clock pulse .phi..sub.d arriving at a certain (longer) time interval. The output voltage V.sub.o of the voltage comparator A.sub.o and an inverted pulse .phi..sub.d formed by inverting the charging and discharging clock pulse signal .phi..sub.d in an inverter L.sub.5 are applied to an AND logic circuit L.sub.6 together with a successively arriving clock pulse signal .phi. of a shorter period. The output V.sub.out of this AND circuit L.sub.6 constitutes the converted output.
Operational principle of this circuit is as follows.
When the charging and discharging clock pulse .phi..sub.d is at a high level "H" ("1" level), the switching transistor Q.sub.o is turned on and hence the charge stored on the capacitor C.sub.o is discharged through the transistor Q.sub.o. If the capacitance C.sub.o is selected to be small, this discharge is achieved relatively rapidly and completely. Then, the terminal voltage of the capacitor C.sub.o becomes zero volts, which is lower than the input voltage V.sub.in. Thus, the comparator A.sub.o generates a high level "H" at the output V.sub.o. Then, when the charging and discharging clock pulse .phi..sub.d becomes of "L" level ("0" level), the inverted output .phi..sub.d becomes of "H" level.
Here, the switching transistor Q.sub.o becomes turned off to cut off the discharging path of the capacitor C.sub.o. Then, the capacitor C.sub.o is gradually charged up by the current from the constant current souce I.sub.o and accordingly the terminal voltage thereof gradually increases. Denoting the period of "L" level of the pulse signal .phi..sub.d as T.sub.d, the maximum terminal voltage V.sub.max of the capacitor C.sub.o is I.sub.o T.sub.d /C.sub.o. During the period t.sub.1 when the clock pulse .phi..sub.d is at the "L" level and when the terminal voltage of the capacitor C.sub.o is lower than the input voltage V.sub.in, the output voltage V.sub.o of the voltage comparator A.sub.o is at the "H" level and hence the AND logic circuit L.sub.6 transmits the waveform of the successively incoming clock pulse .phi. to the output V.sub.out. When the terminal voltage of the capacitor C.sub.o exceeds the input voltage V.sub.in, the relation of the inputs of the voltage comparator A.sub.o is changed. Thus, the output V.sub.o of the comparator A.sub.o is inverted to the "L" level. Therefore, the gate of the AND circuit L.sub.6 is closed and the output V.sub.out thereof is held at the "L" level. Therefore, the analog input voltage can be known by measuring the period t.sub.1 in which the clock pulse .phi. appears or is present at the output V.sub.out or by counting the number of such clock pulses in a counter, etc.
The above converter circuit, however, is accompanied by the following drawbacks.
(1) In the general integration type A-D converter as shown in FIG. 5, the operation of the circuit is based on the period from the time when the capacitor C.sub.o is discharged to zero volts to the time when the capacitor C.sub.o is charged up to the input voltage. Therefore, the charging and discharging operation consumes a certain time period and the conversion speed or the response time becomes slow or long.
(2) Since the transistor Q.sub.o performs repeated on-off operations, there arises the residual voltage. Then, the terminal voltage of the capacitor may not fall completely to the ground level. That is, the ground level differs for each operation. Then, no accurate conversion can be achieved.
(3) The on-resistance of the transistor Q.sub.o has a dispersion from the designed value in manufacture. This leads to different discharging time constant from one transistor to another. When mass-production is employed, the reproducibility is poor and the yield cannot be improved.